112 search results - page 13 / 23 » Microarchitectural exploration with Liberty |
SBACPAD
2004
IEEE
13 years 8 months ago
2004
IEEE
High-performance superscalar processors are designed with the help of complex simulation environment. The simulation infrastructure permits to validate the processor instruction s...
SAMOS
2010
Springer
13 years 5 months ago
2010
Springer
—Instruction set simulators (ISS) are vital tools for compiler and processor architecture design space exploration and verification. State-of-the-art simulators using just-in-ti...
ICPP
2008
IEEE
14 years 1 months ago
2008
IEEE
The issue queue (IQ) is a key microarchitecture structure for exploiting instruction-level and thread-level parallelism in dynamically scheduled simultaneous multithreaded (SMT) p...
HPCA
2002
IEEE
14 years 7 months ago
2002
IEEE
This paper explores the concept of micro-architectural loops and discusses their impact on processor pipelines. In particular, we establish the relationship between loose loops an...
PATMOS
2004
Springer
14 years 23 days ago
2004
Springer
Abstract. An extensible and configurable processor is a programmable platform offering the possibility to customize the instruction set and/or underlying microarchitecture. Efficie...