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DATE
2009
IEEE
81views Hardware» more  DATE 2009»
14 years 2 months ago
ReSim, a trace-driven, reconfigurable ILP processor simulator
— Modern processors are becoming more complex and as features and application size increase, their evaluation is becoming more time-consuming. To date, design space exploration r...
Sotiria Fytraki, Dionisios N. Pnevmatikatos
DATE
2009
IEEE
133views Hardware» more  DATE 2009»
14 years 2 months ago
Architectural support for low overhead detection of memory violations
Violations in memory references cause tremendous loss of productivity, catastrophic mission failures, loss of privacy and security, and much more. Software mechanisms to detect me...
Saugata Ghose, Latoya Gilgeous, Polina Dudnik, Ane...
RTCSA
2009
IEEE
14 years 2 months ago
Branch Target Buffers: WCET Analysis Framework and Timing Predictability
—One step in the verification of hard real-time systems is to determine upper bounds on the worst-case execution times (WCET) of tasks. To obtain tight bounds, a WCET analysis h...
Daniel Grund, Jan Reineke, Gernot Gebhard
ICPP
2009
IEEE
14 years 2 months ago
Exploiting Simulation Slack to Improve Parallel Simulation Speed
Parallel simulation is a technique to accelerate microarchitecture simulation of CMPs by exploiting the inherent parallelism of CMPs. In this paper, we explore the simulation para...
Jianwei Chen, Murali Annavaram, Michel Dubois
ASAP
2008
IEEE
142views Hardware» more  ASAP 2008»
14 years 1 months ago
Managing multi-core soft-error reliability through utility-driven cross domain optimization
As semiconductor processing technology continues to scale down, managing reliability becomes an increasingly difficult challenge in high-performance microprocessor design. Transie...
Wangyuan Zhang, Tao Li