Sciweavers

112 search results - page 21 / 23
» Microarchitectural exploration with Liberty
Sort
View
ISPASS
2005
IEEE
14 years 29 days ago
Measuring Program Similarity: Experiments with SPEC CPU Benchmark Suites
Performance evaluation using only a subset of programs from a benchmark suite is commonplace in computer architecture research. This is especially true during early design space e...
Aashish Phansalkar, Ajay Joshi, Lieven Eeckhout, L...
MICRO
2005
IEEE
136views Hardware» more  MICRO 2005»
14 years 29 days ago
Automatic Thread Extraction with Decoupled Software Pipelining
Until recently, a steadily rising clock rate and other uniprocessor microarchitectural improvements could be relied upon to consistently deliver increasing performance for a wide ...
Guilherme Ottoni, Ram Rangan, Adam Stoler, David I...
MICRO
2005
IEEE
144views Hardware» more  MICRO 2005»
14 years 29 days ago
A Dynamic Compilation Framework for Controlling Microprocessor Energy and Performance
Dynamic voltage and frequency scaling (DVFS) is an effective technique for controlling microprocessor energy and performance. Existing DVFS techniques are primarily based on hardw...
Qiang Wu, Margaret Martonosi, Douglas W. Clark, Vi...
MTV
2005
IEEE
100views Hardware» more  MTV 2005»
14 years 29 days ago
A Study of Architecture Description Languages from a Model-based Perspective
Abstract— Owing to the recent trend of using applicationspecific instruction-set processors (ASIP), many Architecture Description Languages (ADLs) have been created. They specif...
Wei Qin, Sharad Malik
ASPDAC
2005
ACM
113views Hardware» more  ASPDAC 2005»
14 years 28 days ago
Scalable interprocedural register allocation for high level synthesis
Abstract— The success of classical high level synthesis has been limited by the complexity of the applications it can handle, typically not large enough to necessitate the depart...
Rami Beidas, Jianwen Zhu