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TVLSI
2010
13 years 2 months ago
Area and Power Optimization of High-Order Gain Calibration in Digitally-Enhanced Pipelined ADCs
Digital calibration techniques are widely utilized to linearize pipelined analog-to-digital converters (ADCs). However, their power dissipation can be prohibitively high, particula...
Mohammad Taherzadeh-Sani, Anas A. Hamoui
ISLPED
1997
ACM
124views Hardware» more  ISLPED 1997»
13 years 11 months ago
Low power high level synthesis by increasing data correlation
With the increasing performance and density of VLSI circuits as well as the popularity of portable devices such as personal digital assistance, power consumption has emerged as an...
Dongwan Shin, Kiyoung Choi
DAC
2001
ACM
14 years 8 months ago
Speeding Up Control-Dominated Applications through Microarchitectural Customizations in Embedded Processors
We present a methodology for microarchitectural customization of embedded processors by exploiting application information, thus attaining the twin benefits of processor standardi...
Peter Petrov, Alex Orailoglu
HPCA
2009
IEEE
14 years 2 months ago
Soft error vulnerability aware process variation mitigation
As transistor process technology approaches the nanometer scale, process variation significantly affects the design and optimization of high performance microprocessors. Prior stu...
Xin Fu, Tao Li, José A. B. Fortes
ASPDAC
2006
ACM
104views Hardware» more  ASPDAC 2006»
13 years 11 months ago
SAVS: a self-adaptive variable supply-voltage technique for process- tolerant and power-efficient multi-issue superscalar proces
- Technology scaling and sub-wavelength optical lithography is associated with significant process variations. We propose a self-adaptive variable supply-voltage scaling (SAVS) tec...
Hai Li, Yiran Chen, Kaushik Roy, Cheng-Kok Koh