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» Migration in Single Chip Multiprocessors
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ASPLOS
2004
ACM
14 years 1 months ago
Heat-and-run: leveraging SMT and CMP to manage power density through the operating system
Power density in high-performance processors continues to increase with technology generations as scaling of current, clock speed, and device density outpaces the downscaling of s...
Mohamed A. Gomaa, Michael D. Powell, T. N. Vijayku...
HPCC
2005
Springer
14 years 1 months ago
Factory: An Object-Oriented Parallel Programming Substrate for Deep Multiprocessors
Abstract. Recent advances in processor technology such as Simultaneous Multithreading (SMT) and Chip Multiprocessing (CMP) enable parallel processing on a single die. These process...
Scott Schneider, Christos D. Antonopoulos, Dimitri...
SLIP
2006
ACM
14 years 1 months ago
The routability of multiprocessor network topologies in FPGAs
A fundamental difference between ASICs and FPGAs is that wires in ASICs are designed such that it matches the requirements of a particular design. Wire parameters such as: length...
Manuel Saldaña, Lesley Shannon, Paul Chow
ICCD
2007
IEEE
98views Hardware» more  ICCD 2007»
14 years 4 months ago
Evaluating voltage islands in CMPs under process variations
Parameter variations are a major factor causing powerperformance asymmetry in chip multiprocessors. In this paper, we analyze the effects of with-in-die (WID) process variations o...
Abhishek Das, Serkan Ozdemir, Gokhan Memik, Alok N...
MICRO
2010
IEEE
130views Hardware» more  MICRO 2010»
13 years 5 months ago
Pseudo-Circuit: Accelerating Communication for On-Chip Interconnection Networks
As the number of cores on a single chip increases with more recent technologies, a packet-switched on-chip interconnection network has become a de facto communication paradigm for ...
Minseon Ahn, Eun Jung Kim