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ICCAD
2008
IEEE
170views Hardware» more  ICCAD 2008»
14 years 4 months ago
A polynomial time approximation scheme for timing constrained minimum cost layer assignment
Abstract— As VLSI technology enters the nanoscale regime, interconnect delay becomes the bottleneck of circuit performance. Compared to gate delays, wires are becoming increasing...
Shiyan Hu, Zhuo Li, Charles J. Alpert
ICCAD
2006
IEEE
117views Hardware» more  ICCAD 2006»
14 years 4 months ago
Post-routing redundant via insertion and line end extension with via density consideration
- Redundant via insertion and line end extension employed in the post-routing stage are two well known and highly recommended techniques to reduce yield loss due to via failure. Ho...
Kuang-Yao Lee, Ting-Chi Wang, Kai-Yuan Chao
ICDE
2010
IEEE
177views Database» more  ICDE 2010»
14 years 2 months ago
Optimal load shedding with aggregates and mining queries
— To cope with bursty arrivals of high-volume data, a DSMS has to shed load while minimizing the degradation of Quality of Service (QoS). In this paper, we show that this problem...
Barzan Mozafari, Carlo Zaniolo
SIGMOD
2009
ACM
161views Database» more  SIGMOD 2009»
14 years 2 months ago
Dependency-aware reordering for parallelizing query optimization in multi-core CPUs
The state of the art commercial query optimizers employ cost-based optimization and exploit dynamic programming (DP) to find the optimal query execution plan (QEP) without evalua...
Wook-Shin Han, Jinsoo Lee
ICALP
2009
Springer
14 years 2 months ago
Improved Bounds for Speed Scaling in Devices Obeying the Cube-Root Rule
Speed scaling is a power management technique that involves dynamically changing the speed of a processor. This gives rise to dualobjective scheduling problems, where the operating...
Nikhil Bansal, Ho-Leung Chan, Kirk Pruhs, Dmitriy ...
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