A polynomial time approximation scheme for timing constrained minimum cost layer assignment

Abstract— As VLSI technology enters the nanoscale regime, interconnect delay becomes the bottleneck of circuit performance. Compared to gate delays, wires are becoming increasingly resistive which makes it more difficult to propagate signals across the chip. However, more advanced technologies (65nm and 45nm) provide relief as the number of metal layers continues to increase. The wires on the upper metal layers are much less resistive and can be used to drive further and faster than on thin metals. This provides an entirely new dimension to the traditional wire sizing problem, namely, layer assignment for efficient timing closure. Assigning all wires to thick metals improves timing, however, routability of the design may be hurt. The challenge is to assign minimal amount of wires to thick metals to meet timing constraints. In this paper, the minimum cost layer assignment problem is proven to be NP-Complete. As a theoretical solution for NP-complete problems, a polynomial time appro...

• Type: Conference
• Year: 2008
• Where: ICCAD
• Authors: Shiyan Hu, Zhuo Li, Charles J. Alpert
• Keywords: Cost Layer Assignment, Hardware, ICCAD 2008, Layer Assignment Problem, Optimal Layer Assignment