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ENTCS
2008
170views more  ENTCS 2008»
13 years 9 months ago
A Coq Library for Verification of Concurrent Programs
Thanks to recent advances, modern proof assistants now enable verification of realistic sequential programs. However, regarding the concurrency paradigm, previous work essentially...
Reynald Affeldt, Naoki Kobayashi
TWC
2010
13 years 3 months ago
Joint power allocation and relay selection for multiuser cooperative communication
User cooperation, whereby multiple users share their antennas and transmit to a common destination in a collaborative manner, has been shown to be an effective way to achieve spat...
Kanchan G. Vardhe, Daryl Reynolds, Brian D. Woerne...
IPPS
2007
IEEE
14 years 3 months ago
A Study of Design Efficiency with a High-Level Language for FPGAs
Over the years reconfigurable computing devices such as FPGAs have evolved from gate-level glue logic to complex reprogrammable processing architectures. However, the tools used f...
Zain-ul-Abdin, Bertil Svensson
ICCAD
1996
IEEE
119views Hardware» more  ICCAD 1996»
14 years 1 months ago
An algorithm for synthesis of system-level interface circuits
We describe an algorithm for the synthesis and optimization of interface circuits for embedded system components such as microprocessors, memory ASIC, and network subsystems with ...
Ki-Seok Chung, Rajesh K. Gupta, C. L. Liu
VTS
1996
IEEE
111views Hardware» more  VTS 1996»
14 years 29 days ago
Synthesis-for-scan and scan chain ordering
Designing a testable circuit is often a two step process. First, the circuit is designed to conform to the functional specifications. Then, the testability aspects are added. By t...
Robert B. Norwood, Edward J. McCluskey