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VTS
2002
IEEE
138views Hardware» more  VTS 2002»
14 years 12 days ago
Test Power Reduction through Minimization of Scan Chain Transitions
Parallel test application helps reduce the otherwise considerable test times in SOCs; yet its applicability is limited by average and peak power considerations. The typical test v...
Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailog...
JSAC
2007
63views more  JSAC 2007»
13 years 7 months ago
A new survivable mapping problem in IP-over-WDM networks
— We introduce a new version of the widely studied survivable mapping problem in IP-over-WDM networks. The new problem allows augmenting the given logical topology and is describ...
Chang Liu, Lu Ruan
ACS
2008
13 years 7 months ago
On Minimal Coalgebras
Abstract. We define an out-degree for F-coalgebras and show that the coalgebras of outdegree at most form a covariety. As a subcategory of all Fcoalgebras, this class has a termin...
H. Peter Gumm
FOSSACS
2005
Springer
14 years 1 months ago
From Separation Logic to First-Order Logic
Separation logic is a spatial logic for reasoning locally about heap structures. A decidable fragment of its assertion language was presented in [1], based on a bounded model prope...
Cristiano Calcagno, Philippa Gardner, Matthew Hagu...
ISMVL
1999
IEEE
76views Hardware» more  ISMVL 1999»
13 years 11 months ago
Multiple-Valued Minimization to Optimize PLAs with Output EXOR Gates
This paper considers an optimization method of programmable logic arrays (PLAs), which have two-input EXOR gate at the outputs. The PLA realizes an EXOR of two sum-of-products exp...
Debatosh Debnath, Tsutomu Sasao