Most research to date on energy minimization in DSP processors has focuses on hardware solution. This paper examines the software-based factors affecting performance and energy co...
In this paper we present an energy efficient framework for processing spatial alarms on mobile clients, while maintaining low computation and storage costs. Our approach to spatia...
—This paper studies the important interaction between parallelization and energy consumption in a parallelizable application. Given the ratio of serial and parallel portion in an...
Leakage energy consumption is an increasing concern in current and future CMOS technologygenerations. Procrastination scheduling, where task execution can be delayed to maximize t...
Abstract. The novel design of high-speed and low-energy FPGA routing architecture consisting of appropriate wire segments and multiple Switch Boxes is introduced. For that purpose,...