769 search results - page 47 / 154 » Minimizing system modification in an incremental design appr... |
DAC
2005
ACM
14 years 9 months ago
2005
ACM
In many of embedded systems, particularly for those with high data computations, the delay of memory access is one of the major bottlenecks in the system's performance. It ha...
DATE
2004
IEEE
13 years 11 months ago
2004
IEEE
In this paper, we present various challenges that arise in the delivery and exchange of multimedia information to mobile devices. Specifically, we focus on techniques for maintain...
VLSID
2007
IEEE
14 years 8 months ago
2007
IEEE
Crosstalk noise in the clock network of digital circuits is often detected late in the design cycle, sometimes as late as after first silicon. It is therefore necessary to fix cros...
DATE
2000
IEEE
14 years 10 days ago
2000
IEEE
Novel methodology and algorithms to seamlessly integrate logic synthesis and physical placement through a transformational approach are presented. Contrary to most placement algor...
IPCCC
2006
IEEE
14 years 1 months ago
2006
IEEE
Low power has been considered as an important issue in instruction cache (I-cache) designs. Several studies have shown that the I-cache can be tuned to reduce power. These techniq...