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HIPC
1999
Springer
14 years 1 months ago
Microcaches
We describe a radically new cache architecture and demonstrate that it offers a huge reduction in cache cost, size and power consumption whilst maintaining performance on a wide ra...
David May, Dan Page, James Irwin, Henk L. Muller
SIGARCH
2008
96views more  SIGARCH 2008»
13 years 9 months ago
Towards hybrid last level caches for chip-multiprocessors
As CMP platforms are widely adopted, more and more cores are integrated on to the die. To reduce the off-chip memory access, the last level cache is usually organized as a distribu...
Li Zhao, Ravi Iyer, Mike Upton, Don Newell
ICCD
2005
IEEE
114views Hardware» more  ICCD 2005»
14 years 6 months ago
Memory Bank Predictors
Cache memories are commonly implemented through multiple memory banks to improve bandwidth and latency. The early knowledge of the data cache bank that an instruction will access ...
Stefan Bieschewski, Joan-Manuel Parcerisa, Antonio...
IPPS
2010
IEEE
13 years 7 months ago
Multicore-aware reuse distance analysis
This paper presents and validates methods to extend reuse distance analysis of application locality characteristics to shared-memory multicore platforms by accounting for invalidat...
Derek L. Schuff, Benjamin S. Parsons, Vijay S. Pai
ICDCS
2000
IEEE
14 years 1 months ago
An Efficient Cache Maintenance Scheme for Mobile Environment
In this paper we present a new cache maintenance scheme, called AS, suitable for wireless mobile environment. Our scheme integrates mobility management scheme of Mobile IP with ca...
Anurag Kahol, Ramandeep Singh Khurana, Sandeep K. ...