446 search results - page 34 / 90 » Modal Logics for Timed Control |
GLVLSI
2008
IEEE
14 years 3 months ago
2008
IEEE
Timing optimizations during logic synthesis has become a necessary step to achieve timing closure in VLSI designs. This often involves “shortening” all paths found in the circ...
ETFA
2006
IEEE
14 years 3 months ago
2006
IEEE
♦ To increase the amount of logic available to the users in SRAM-based FPGAs, manufacturers are using nanometric technologies to boost logic density and reduce costs, making its ...
FOSSACS
2000
Springer
14 years 19 days ago
2000
Springer
Abstract. This paper develops a highly expressive semantic framework for program refinement that supports both temporal reasoning and reasoning about the knowledge of a single agen...
FTCS
1994
13 years 10 months ago
1994
This paper examines architectural techniques for providing concurrent error detection in self-timed VLSI pipelines. Signal pairs from Differential Cascode Voltage Switch Logic are...
DLOG
2003
13 years 10 months ago
2003
In this chapter, we are concerned with the relationship between Description Logics and other formalisms, regardless of whether they were designed for knowledge representation issu...