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TII
2010
124views Education» more  TII 2010»
13 years 3 months ago
Address-Independent Estimation of the Worst-case Memory Performance
Abstract--Real-time systems are subject to temporal constraints and require a schedulability analysis to ensure that task execution finishes within lower and upper specified bounds...
Basilio B. Fraguela, Diego Andrade, Ramon Doallo
IPPS
2010
IEEE
13 years 6 months ago
Speculative execution on multi-GPU systems
Abstract--The lag of parallel programming models and languages behind the advance of heterogeneous many-core processors has left a gap between the computational capability of moder...
Gregory F. Diamos, Sudhakar Yalamanchili
CODES
2004
IEEE
14 years 21 days ago
Fast exploration of bus-based on-chip communication architectures
As a result of improvements in process technology, more and more components are being integrated into a single System-on-Chip (SoC) design. Communication between these components ...
Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdha...
WCRE
2006
IEEE
14 years 3 months ago
Animated Visualization of Software History using Evolution Storyboards
The understanding of the structure of a software system can be improved by analyzing the system’s evolution during development. Visualizations of software history that provide o...
Dirk Beyer, Ahmed E. Hassan
HPDC
2010
IEEE
13 years 10 months ago
A hybrid Markov chain model for workload on parallel computers
This paper proposes a comprehensive modeling architecture for workloads on parallel computers using Markov chains in combination with state dependent empirical distribution functi...
Anne Krampe, Joachim Lepping, Wiebke Sieben