Declarative modelling approaches in principle assume a notion of representation or representational content for the modelling concepts. The notion of representational content as di...
The outcome of verifying software is often a `counterexample', i.e., a listing of the actions and states of a behavior not satisfying the specification. In order to understan...
A logic model checker can be an effective tool for debugging software applications. A stumbling block can be that model checking tools expect the user to supply a formal statement...
Margaret H. Smith, Gerard J. Holzmann, Kousha Etes...
We present a formal verification methodology that we have used on a computer system design project. The methodology integrates a temporal logic model checker with a conventional pr...
System level modeling with executable languages such as C/C++ has been crucial in the development of large electronic systems from general processors to application specific desig...
Xi Chen, Yan Luo, Harry Hsieh, Laxmi N. Bhuyan, Fe...