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» Model Reuse through Hardware Design Patterns
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IEEEPACT
2007
IEEE
14 years 1 months ago
Automatic Correction of Loop Transformations
Loop nest optimization is a combinatorial problem. Due to the growing complexity of modern architectures, it involves two increasingly difficult tasks: (1) analyzing the profita...
Nicolas Vasilache, Albert Cohen, Louis-Noël P...
ISLPED
2004
ACM
122views Hardware» more  ISLPED 2004»
14 years 24 days ago
Microarchitectural techniques for power gating of execution units
Leakage power is a major concern in current and future microprocessor designs. In this paper, we explore the potential of architectural techniques to reduce leakage through power-...
Zhigang Hu, Alper Buyuktosunoglu, Viji Srinivasan,...
CIDR
2007
144views Algorithms» more  CIDR 2007»
13 years 8 months ago
Cache-Oblivious Query Processing
We propose a radical approach to relational query processing that aims at automatically and consistently achieving a good performance on any memory hierarchy. We believe this auto...
Bingsheng He, Qiong Luo
SASP
2009
IEEE
291views Hardware» more  SASP 2009»
14 years 2 months ago
FCUDA: Enabling efficient compilation of CUDA kernels onto FPGAs
— As growing power dissipation and thermal effects disrupted the rising clock frequency trend and threatened to annul Moore’s law, the computing industry has switched its route...
Alexandros Papakonstantinou, Karthik Gururaj, John...
VALUETOOLS
2006
ACM
167views Hardware» more  VALUETOOLS 2006»
14 years 1 months ago
Detailed cache simulation for detecting bottleneck, miss reason and optimization potentialities
Cache locality optimization is an efficient way for reducing the idle time of modern processors in waiting for needed data. This kind of optimization can be achieved either on the...
Jie Tao, Wolfgang Karl