288 search results - page 29 / 58 » Model checking SystemC designs using timed automata |
COMPSAC
2009
IEEE
14 years 1 months ago
2009
IEEE
Along with the popularity of software-intensive systems, the interactions between system components and between humans and software applications are becoming more and more complex...
FORMATS
2004
Springer
14 years 5 days ago
2004
Springer
We propose an effective and complete method for verifying safety and properties of timed systems, which is based on predicate abstraction for g finite abstractions of timed autom...
DATE
2010
IEEE
13 years 11 months ago
2010
IEEE
Model checking techniques are promising for automated generation of directed tests. However, due to the prohibitively large time and resource requirements, conventional model chec...
DATE
2009
IEEE
14 years 1 months ago
2009
IEEE
—Verification is a major issue in circuit and system design. Formal methods like bounded model checking (BMC) can guarantee a high quality of the verification. There are severa...
ISQED
2003
IEEE
14 years 1 days ago
2003
IEEE
This paper describes the use of integer equations for high level modeling digital circuits for application of formal verification properties at this level. Most formal verificatio...