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» Model checking SystemC designs using timed automata
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SPIN
2000
Springer
13 years 10 months ago
Verification and Optimization of a PLC Control Schedule
Abstract. We report on the use of model checking techniques for both the verification of a process control program and the derivation of optimal control schedules. Most of this wor...
Ed Brinksma, Angelika Mader
ICDE
2008
IEEE
139views Database» more  ICDE 2008»
14 years 8 months ago
Simultaneous Equation Systems for Query Processing on Continuous-Time Data Streams
We introduce Pulse, a framework for processing continuous queries over models of continuous-time data, which can compactly and accurately represent many real-world activities and p...
Jennie Rogers, Olga Papaemmanouil, Ugur Çet...
VLSID
2010
IEEE
155views VLSI» more  VLSID 2010»
13 years 4 months ago
Synchronized Generation of Directed Tests Using Satisfiability Solving
Directed test generation is important for the functional verification of complex system-on-chip designs. SAT based bounded model checking is promising for counterexample generatio...
Xiaoke Qin, Mingsong Chen, Prabhat Mishra
ISORC
2005
IEEE
14 years 9 days ago
RMMC Programming Model and Support Execution Engine in the TMO Programming Scheme
: While the conventional remote method invocation mechanism has been considered for a long time as the primary approach for facilitating interactions among real-time objects, a mul...
K. H. (Kane) Kim, Yuqing Li, Sheng Liu, Moon-hae K...
JSA
2008
74views more  JSA 2008»
13 years 6 months ago
Resource conflict detection in simulation of function unit pipelines
Processor simulators are important parts of processor design toolsets in which they are used to verify and evaluate the properties of the designed processors. While simulating arch...
Pekka Jääskeläinen, Vladimír...