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» Model checking transactional memories
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CAV
2010
Springer
179views Hardware» more  CAV 2010»
13 years 11 months ago
Generating Litmus Tests for Contrasting Memory Consistency Models
Well-defined memory consistency models are necessary for writing correct parallel software. Developing and understanding formal specifications of hardware memory models is a chal...
Sela Mador-Haim, Rajeev Alur, Milo M. K. Martin
ICTAC
2009
Springer
13 years 5 months ago
A First-Order Policy Language for History-Based Transaction Monitoring
Online trading invariably involves dealings between strangers, so it is important for one party to be able to judge objectively the trustworthiness of the other. In such a setting,...
Andreas Bauer 0002, Rajeev Goré, Alwen Tiu
DATE
2008
IEEE
168views Hardware» more  DATE 2008»
14 years 2 months ago
Cycle-approximate Retargetable Performance Estimation at the Transaction Level
This paper presents a novel cycle-approximate performance estimation technique for automatically generated transaction level models (TLMs) for heterogeneous multicore designs. The...
Yonghyun Hwang, Samar Abdi, Daniel Gajski
DAC
1998
ACM
14 years 8 months ago
Functional Vector Generation for HDL Models Using Linear Programming and 3-Satisfiability
Abstract-Our strategy for automatic generation of functional vectors is based on exercising selected paths in the given hardware description language (HDL) model. The HDL model des...
Farzan Fallah, Srinivas Devadas, Kurt Keutzer
SAT
2005
Springer
123views Hardware» more  SAT 2005»
14 years 1 months ago
Bounded Model Checking with QBF
Current algorithms for bounded model checking (BMC) use SAT methods for checking satisfiability of Boolean formulas. These BMC methods suffer from a potential memory explosion prob...
Nachum Dershowitz, Ziyad Hanna, Jacob Katz