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» Model design using hierarchical web-based libraries
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ICCAD
2005
IEEE
176views Hardware» more  ICCAD 2005»
14 years 4 months ago
Statistical gate sizing for timing yield optimization
— Variability in the chip design process has been relatively increasing with technology scaling to smaller dimensions. Using worst case analysis for circuit optimization severely...
Debjit Sinha, Narendra V. Shenoy, Hai Zhou
SAC
2006
ACM
14 years 1 months ago
Building the functional performance model of a processor
In this paper, we present an efficient procedure for building a piecewise linear function approximation of the speed function of a processor with hierarchical memory structure. Th...
Alexey L. Lastovetsky, Ravi Reddy, Robert Higgins
INFOCOM
2007
IEEE
14 years 2 months ago
Realistic Sensing Area Modeling
—Despite the well-known fact that sensing patterns in reality are highly irregular, researchers continue to develop protocols with simplifying assumptions about the sensing. For ...
Joengmin Hwang, Yu Gu, Tian He, Yongdae Kim
IPSN
2004
Springer
14 years 1 months ago
Modeling of sensor nets in Ptolemy II
This paper describes a modeling and simulation framework called VisualSense for wireless sensor networks that builds on and leverages Ptolemy II. This framework supports actor-ori...
Philip Baldwin, Sanjeev Kohli, Edward A. Lee, Xiao...
DSRT
2002
IEEE
14 years 21 days ago
Nautilus - The Environment for Training and Testing
The paper describes an experimental web-based environment for teaching and testing. The application named Nautilus has been developed using Virtual Reality Modeling Language (VRML...
Jiri Chludil, Jiri Zara