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ISQED
2008
IEEE
153views Hardware» more  ISQED 2008»
14 years 3 months ago
Accelerating Clock Mesh Simulation Using Matrix-Level Macromodels and Dynamic Time Step Rounding
Clock meshes have found increasingly wide applications in today’s high-performance IC designs. The inherent routing redundancies associated with clock meshes lead to improved cl...
Xiaoji Ye, Min Zhao, Rajendran Panda, Peng Li, Jia...
EMSOFT
2007
Springer
14 years 3 months ago
Virtual execution of AADL models via a translation into synchronous programs
Architecture description languages are used to describe both the hardware and software architecture of an application, at system-level. The basic software components are intended ...
Erwan Jahier, Nicolas Halbwachs, Pascal Raymond, X...
GECCO
2007
Springer
179views Optimization» more  GECCO 2007»
14 years 3 months ago
A destructive evolutionary process: a pilot implementation
This paper describes the application of evolutionary search to the problem of Flash memory wear-out. The operating parameters of Flash memory are notoriously difficult to determin...
Joe Sullivan, Conor Ryan
ICS
2007
Tsinghua U.
14 years 3 months ago
Optimization of data prefetch helper threads with path-expression based statistical modeling
This paper investigates helper threads that improve performance by prefetching data on behalf of an application’s main thread. The focus is data prefetch helper threads that lac...
Tor M. Aamodt, Paul Chow
DATE
2006
IEEE
104views Hardware» more  DATE 2006»
14 years 3 months ago
Integrated placement and skew optimization for rotary clocking
—The clock distribution network is a key component of any synchronous VLSI design. High power dissipation and pressure volume temperature-induced variations in clock skew have st...
Ganesh Venkataraman, Jiang Hu, Frank Liu, Cliff C....