117 search results - page 2 / 24 » Model-integrated parallel application synthesis |
DSD
2010
IEEE
13 years 6 months ago
2010
IEEE
—We propose a parametrized memory template for applications with parallel for loops. The template’s parameters reflect important trade-offs made during system design. The temp...
ARC
2008
Springer
13 years 9 months ago
2008
Springer
Abstract. In this paper, we present the PARO design tool for the automated hardware synthesis of massively parallel embedded architectures for given dataflow dominant applications....
SASP
2008
IEEE
14 years 1 months ago
2008
IEEE
Different approaches have been proposed over the years for automatically transforming High-Level-Languages (HLL) descriptions of applications into custom hardware implementations. ...
EUROPAR
1999
Springer
13 years 11 months ago
1999
Springer
A fully adaptive router with hybrid bu ers at the input and output channels was designed, which improves the throughput of its input bu er counterpart by up to 40% and has only 10%...
CORR
2010
Springer
13 years 4 months ago
2010
Springer
This paper focuses on the performance evaluation of the parallel manipulators for milling of composite materials. For this application the most significant performance measurement...