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» Modeling Cache Effects at the Transaction Level
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CODES
2009
IEEE
14 years 1 months ago
Using binary translation in event driven simulation for fast and flexible MPSoC simulation
In this paper, we investigate the use of instruction set simulators (ISS) based on binary translation to accelerate full timed multiprocessor system simulation at transaction leve...
Marius Gligor, Nicolas Fournel, Frédé...
ISPASS
2008
IEEE
14 years 1 months ago
Pinpointing and Exploiting Opportunities for Enhancing Data Reuse
—The potential for improving the performance of data-intensive scientific programs by enhancing data reuse in cache is substantial because CPUs are significantly faster than me...
Gabriel Marin, John M. Mellor-Crummey
WSC
2000
13 years 8 months ago
Inventory management simulations at Cat Logistics
Simulation is used extensively by Caterpillar Logistics Services, Inc. (Cat Logistics) to determine an appropriate strategy for achieving clients' inventory and customer serv...
C. Ann Goodsell, Thomas J. Van Kley
PE
2010
Springer
175views Optimization» more  PE 2010»
13 years 1 months ago
Generalized ERSS tree model: Revisiting working sets
Accurately characterizing the resource usage of an application at various levels in the memory hierarchy has been a long-standing research problem. Existing characterization studi...
Ricardo Koller, Akshat Verma, Raju Rangaswami
CODES
2004
IEEE
13 years 10 months ago
Fast exploration of bus-based on-chip communication architectures
As a result of improvements in process technology, more and more components are being integrated into a single System-on-Chip (SoC) design. Communication between these components ...
Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdha...