59 search results - page 7 / 12 » Modeling Cache Effects at the Transaction Level |
CIKM
2001
Springer
14 years 1 days ago
2001
Springer
As mobile devices get ubiquitous and grow in computational power, their management of interdependent data also becomes increasingly important. The mobile environment exhibits all ...
MEMOCODE
2010
IEEE
13 years 5 months ago
2010
IEEE
Electronic System Level (ESL) design manages the complexity of todays systems by using abstract models. In this context Transaction Level Modeling (TLM) is state-of-theart for desc...
ISCA
2010
IEEE
13 years 9 months ago
2010
IEEE
This paper explores the design space of MMU caches that accelerate virtual-to-physical address translation in processor architectures, such as x86-64, that use a radix tree page t...
ANSS
2004
IEEE
13 years 11 months ago
2004
IEEE
One important issue that has to be taken into account in wireless devices is the energy conservation. Every infrastructureless network must be adaptively self configured particula...
IPPS
2000
IEEE
13 years 12 months ago
2000
IEEE
Effective utilization of cache memories is a key factor in achieving high performance in computing the Discrete Fourier Transform (DFT). Most optimizationtechniques for computing ...