356 search results - page 25 / 72 » Modeling Cache Sharing on Chip Multiprocessor Architectures |
ICS
2010
Tsinghua U.
13 years 11 months ago
2010
Tsinghua U.
The growing influence of wire delay in cache design has meant that access latencies to last-level cache banks are no longer constant. Non-Uniform Cache Architectures (NUCAs) have ...
ICCAD
2003
IEEE
14 years 5 months ago
2003
IEEE
Recent efforts in adapting computer networks into system-on-chip (SOC), or network-on-chip, present a setback to the traditional computer systems for the lack of effective program...
ECRTS
2008
IEEE
14 years 3 months ago
2008
IEEE
Multicore architectures, which have multiple processing units on a single chip, have been adopted by most chip manufacturers. Most such chips contain on-chip caches that are share...
CF
2006
ACM
14 years 10 days ago
2006
ACM
Traditionally, cache coherence in large-scale shared-memory multiprocessors has been ensured by means of a distributed directory structure stored in main memory. In this way, the ...
HPCA
2003
IEEE
14 years 9 months ago
2003
IEEE
Scalability of applications on distributed sharedmemory (DSM) multiprocessors is limited by communication overheads. At some point, using more processors to increase parallelism y...