356 search results - page 37 / 72 » Modeling Cache Sharing on Chip Multiprocessor Architectures |
IPPS
2000
IEEE
14 years 1 months ago
2000
IEEE
In this paper, we propose a novel hardware caching technique, called switch directory, to reduce the communication latency in CC-NUMA multiprocessors. The main idea is to implemen...
DATE
2006
IEEE
14 years 2 months ago
2006
IEEE
NoC architectures can be adopted to support general communications among multiple IPs over multi-processor Systems on Chip (SoCs). In this work we illustrate the modeling and simu...
ISCA
2010
IEEE
13 years 10 months ago
2010
IEEE
Two broad classes of memory models are available today: models with hardware cache coherence, used in conventional chip multiprocessors, and models that rely upon software to mana...
DDECS
2006
IEEE
14 years 2 months ago
2006
IEEE
—The impact of shared instruction memory on performance is measured and analyzed for an FPGAbased Multiprocessor System-on-Chip (MP-SoC) with an MPEG-4 video encoding application...
MSE
2002
IEEE
14 years 1 months ago
2002
IEEE
This paper presents the study of running several core multimedia applications on a simultaneous multithreading (SMT) architecture and derives design principles for multimedia soft...