Sciweavers

356 search results - page 42 / 72
» Modeling Cache Sharing on Chip Multiprocessor Architectures
Sort
View
ICS
2004
Tsinghua U.
14 years 2 months ago
CQoS: a framework for enabling QoS in shared caches of CMP platforms
Cache hierarchies have been traditionally designed for usage by a single application, thread or core. As multi-threaded (MT) and multi-core (CMP) platform architectures emerge and...
Ravi R. Iyer
CCECE
2006
IEEE
14 years 2 months ago
QOS Driven Network-on-Chip Design for Real Time Systems
Real Time embedded system designers are facing extreme challenges in underlying architectural design selection. It involves the selection of a programmable, concurrent, heterogene...
Ankur Agarwal, Mehmet Mustafa, Abhijit S. Pandya
WWW
2005
ACM
14 years 9 months ago
A multi-threaded PIPELINED Web server architecture for SMP/SoC machines
Design of high performance Web servers has become a recent research thrust to meet the increasing demand of networkbased services. In this paper, we propose a new Web server archi...
Gyu Sang Choi, Jin-Ha Kim, Deniz Ersoz, Chita R. D...
STOC
1993
ACM
264views Algorithms» more  STOC 1993»
14 years 22 days ago
Contention in shared memory algorithms
Most complexity measures for concurrent algorithms for asynchronous shared-memory architectures focus on process steps and memory consumption. In practice, however, performance of ...
Cynthia Dwork, Maurice Herlihy, Orli Waarts
DATE
2008
IEEE
155views Hardware» more  DATE 2008»
14 years 3 months ago
Comparison of memory write policies for NoC based Multicore Cache Coherent Systems
The following study shows a direct comparison of memory write policies in Shared Memory Multicore Systems. Although there are much work and many studies about this issue, our work...
Pierre Guironnet de Massas, Frédéric...