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» Modeling Cache Sharing on Chip Multiprocessor Architectures
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SPAA
1990
ACM
14 years 21 days ago
Analysis of Multithreaded Architectures for Parallel Computing
Multithreading has been proposed as an architectural strategy for tolerating latency in multiprocessors and, through limited empirical studies, shown to offer promise. This paper ...
Rafael H. Saavedra-Barrera, David E. Culler, Thors...
DAC
1996
ACM
14 years 25 days ago
Experience in Designing a Large-scale Multiprocessor using Field-Programmable Devices and Advanced CAD Tools
This paper provides a case study that shows how a demanding application stresses the capabilities of today's CAD tools, especially in the integration of products from multipl...
Stephen Dean Brown, Naraig Manjikian, Zvonko G. Vr...
HPCA
2009
IEEE
14 years 9 months ago
Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy
Cache hierarchies in future many-core processors are expected to grow in size and contribute a large fraction of overall processor power and performance. In this paper, we postula...
Niti Madan, Li Zhao, Naveen Muralimanohar, Anirudd...
HIPS
1998
IEEE
14 years 28 days ago
Implementing Automatic Coordination on Networks of Workstations
Distributed shared objects are a well known approach to achieve independenceof the memory model for parallel programming. The illusion of shared (global) objects is a conabstracti...
Christian Weiß, Jürgen Knopp, Hermann H...
ASPLOS
2009
ACM
14 years 9 months ago
Accelerating critical section execution with asymmetric multi-core architectures
To improve the performance of a single application on Chip Multiprocessors (CMPs), the application must be split into threads which execute concurrently on multiple cores. In mult...
M. Aater Suleman, Onur Mutlu, Moinuddin K. Qureshi...