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» Modeling Cache Sharing on Chip Multiprocessor Architectures
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CAL
2010
13 years 5 months ago
SMT-Directory: Efficient Load-Load Ordering for SMT
Memory models like SC, TSO, and PC enforce load-load ordering, requiring that loads from any single thread appear to occur in program order to all other threads. Out-of-order execu...
A. Hilton, A. Roth
SOSP
1997
ACM
13 years 10 months ago
Towards Transparent and Efficient Software Distributed Shared Memory
Despite a large research effort, software distributed shared memory systems have not been widely used to run parallel applications across clusters of computers. The higher perform...
Daniel J. Scales, Kourosh Gharachorloo
P2P
2003
IEEE
110views Communications» more  P2P 2003»
14 years 1 months ago
Range Addressable Network: A P2P Cache Architecture for Data Ranges
Peer-to-peer computing paradigm is emerging as a scalable and robust model for sharing media objects. In this paper, we propose an architecture and describe the associated algorit...
Anshul Kothari, Divyakant Agrawal, Abhishek Gupta,...
DAC
2010
ACM
13 years 9 months ago
A correlation-based design space exploration methodology for multi-processor systems-on-chip
Given the increasing complexity of multi-processor systems-onchip, a wide range of parameters must be tuned to find the best trade-offs in terms of the selected system figures of ...
Giovanni Mariani, Aleksandar Brankovic, Gianluca P...
DAC
2006
ACM
13 years 10 months ago
A fast HW/SW FPGA-based thermal emulation framework for multi-processor system-on-chip
With the growing complexity in consumer embedded products and the improvements in process technology, Multi-Processor SystemOn-Chip (MPSoC) architectures have become widespread. T...
David Atienza, Pablo Garcia Del Valle, Giacomo Pac...