356 search results - page 68 / 72 » Modeling Cache Sharing on Chip Multiprocessor Architectures |
VLSID
2006
IEEE
14 years 2 months ago
2006
IEEE
This tutorial focuses on advanced techniques to cope with the complexity of designing modern digital chips which are complete systems often containing multiple processors, complex...
HPCA
1998
IEEE
14 years 1 months ago
1998
IEEE
The performance of a concurrent multithreaded architectural model, called superthreading 15 , is studied in this paper. It tries to integrate optimizing compilation techniques and...
CODES
2009
IEEE
14 years 1 months ago
2009
IEEE
Performance estimation of Multi-Processor System-On-Chip (MPa high abstraction level is required in order to perform early architecture exploration and accurate design validations...
DAC
2006
ACM
14 years 9 months ago
2006
ACM
Networks-on-Chip (NoC) architectures provide a scalable solution to on-chip communication problem but the bandwidth offered by NoCs can be utilized efficiently only in presence of...
PPOPP
1997
ACM
14 years 28 days ago
1997
ACM
Global addressing of shared data simplifies parallel programming and complements message passing models commonly found in distributed memory machines. A number of programming sys...