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DATE
2005
IEEE
134views Hardware» more  DATE 2005»
14 years 4 months ago
Assertion-Based Design Exploration of DVS in Network Processor Architectures
With the scaling of technology and higher requirements on performance and functionality, power dissipation is becoming one of the major design considerations in the development of...
Jia Yu, Wei Wu, Xi Chen, Harry Hsieh, Jun Yang 000...
ICML
1994
IEEE
14 years 2 months ago
A Modular Q-Learning Architecture for Manipulator Task Decomposition
Compositional Q-Learning (CQ-L) (Singh 1992) is a modular approach to learning to performcomposite tasks made up of several elemental tasks by reinforcement learning. Skills acqui...
Chen K. Tham, Richard W. Prager
JSA
2006
113views more  JSA 2006»
13 years 11 months ago
A power-efficient TCAM architecture for network forwarding tables
Stringent memory access and search speed requirements are two of the main bottlenecks in wire speed processing. Most viable search engines are implemented in content addressable m...
Taskin Koçak, Faysal Basci
FCCM
2004
IEEE
144views VLSI» more  FCCM 2004»
14 years 2 months ago
Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine
In this paper we present a novel use of an FPGA as a computing element for streaming based application. We investigate the virtualized execution of dynamic reconfigurable tasks. We...
Matthias Dyer, Marco Platzner, Lothar Thiele
CLEIEJ
2008
88views more  CLEIEJ 2008»
13 years 11 months ago
A Trust Model for a Group of E-mail Servers
E-mail services are essential in the Internet. However, the current e-mail architecture presents problems that open it to several threats. Alternatives have been proposed to solve...
Leonardo de Oliveira, Carlos Maziero