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ASPDAC
2008
ACM
104views Hardware» more  ASPDAC 2008»
13 years 9 months ago
Low power clock buffer planning methodology in F-D placement for large scale circuit design
Traditionally, clock network layout is performed after cell placement. Such methodology is facing a serious problem in nanometer IC designs where people tend to use huge clock buff...
Yanfeng Wang, Qiang Zhou, Yici Cai, Jiang Hu, Xian...
SENSYS
2010
ACM
13 years 5 months ago
Enix: a lightweight dynamic operating system for tightly constrained wireless sensor platforms
Enix is a lightweight dynamic operating system for tightly constrained platforms for wireless sensor networks (WSN). Enix provides a cooperative threading model, which is applicab...
Yu-Ting Chen, Ting-Chou Chien, Pai H. Chou
EMSOFT
2005
Springer
14 years 26 days ago
Passive mid-stream monitoring of real-time properties
Passive monitoring or testing of complex systems and networks running in the field can provide valuable insights into their behavior in actual environments of use. In certain con...
Lalita Jategaonkar Jagadeesan, Ramesh Viswanathan
VISUALIZATION
1992
IEEE
13 years 11 months ago
Display of Scientific Data Structures for Algorithm Visualization
algorithms as networks of modules. The data flow architecture is popular because of the flexibility of mixing calculation modules with display modules, and because of its easy grap...
William L. Hibbard, Charles R. Dyer, Brian E. Paul
ICPADS
2008
IEEE
14 years 1 months ago
Dynamic Resource Allocation in Enterprise Systems
It is common that Internet service hosting centres use several logical pools to assign server resources to different applications, and that they try to achieve the highest total r...
James Wen Jun Xue, Adam P. Chester, Ligang He, Ste...