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IPPS
1996
IEEE
13 years 11 months ago
A Virtual Memory Model for Parallel Supercomputers
A model for virtual memory in a distributed memory parallel computer is proposed. It uses a novel parallel computing operating system framework and leads to the definition of two ...
Veronica L. M. Reis, Isaac D. Scherson
ISQED
2010
IEEE
126views Hardware» more  ISQED 2010»
13 years 9 months ago
Modeling and verification of industrial flash memories
We present a method to abstract, formalize, and verify industrial flash memory implementations. Flash memories contain specialized transistors, e.g., floating gate and split gate d...
Sandip Ray, Jayanta Bhadra, Thomas Portlock, Ronal...
TACAS
1998
Springer
98views Algorithms» more  TACAS 1998»
13 years 11 months ago
Efficient Modeling of Memory Arrays in Symbolic Ternary Simulation
This paper enables symbolic ternary simulation of systems with large embedded memories. Each memory array is replaced with a behavioral model, where the number of symbolic variable...
Miroslav N. Velev, Randal E. Bryant
ICCAD
2008
IEEE
125views Hardware» more  ICCAD 2008»
14 years 4 months ago
A succinct memory model for automated design debugging
— In today’s complex SoC designs, verification and debugging are becoming ever more crucial and increasingly timeconsuming tasks. The prevalence of embedded memories adds to t...
Brian Keng, Hratch Mangassarian, Andreas G. Veneri...
CAV
2010
Springer
179views Hardware» more  CAV 2010»
13 years 11 months ago
Generating Litmus Tests for Contrasting Memory Consistency Models
Well-defined memory consistency models are necessary for writing correct parallel software. Developing and understanding formal specifications of hardware memory models is a chal...
Sela Mador-Haim, Rajeev Alur, Milo M. K. Martin