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CGO
2006
IEEE
14 years 2 months ago
A Cross-Architectural Interface for Code Cache Manipulation
Software code caches help amortize the overhead of dynamic binary transformation by enabling reuse of transformed code. Since code caches contain a potentiallyaltered copy of ever...
Kim M. Hazelwood, Robert S. Cohn
INFOCOM
2006
IEEE
14 years 2 months ago
Mobile Emulab: A Robotic Wireless and Sensor Network Testbed
Abstract— Simulation has been the dominant research methodology in wireless and sensor networking. When mobility is added, real-world experimentation is especially rare. However,...
David Johnson, Tim Stack, Russ Fish, Daniel Montra...
MEMOCODE
2006
IEEE
14 years 2 months ago
Latency-insensitive design and central repetitive scheduling
The theory of latency-insensitive design (LID) was recently invented to cope with the time closure problem in otherwise synchronous circuits and programs. The idea is to allow the...
Julien Boucaron, Robert de Simone, Jean-Vivien Mil...
MICRO
2006
IEEE
145views Hardware» more  MICRO 2006»
14 years 2 months ago
Virtually Pipelined Network Memory
We introduce virtually-pipelined memory, an architectural technique that efficiently supports high-bandwidth, uniform latency memory accesses, and high-confidence throughput eve...
Banit Agrawal, Timothy Sherwood
CF
2006
ACM
14 years 2 months ago
Dynamic thread assignment on heterogeneous multiprocessor architectures
In a multi-programmed computing environment, threads of execution exhibit different runtime characteristics and hardware resource requirements. Not only do the behaviors of distin...
Michela Becchi, Patrick Crowley
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