78 search results - page 6 / 16 » Modeling QCA for area minimization in logic synthesis |
ITC
1995
IEEE
14 years 18 days ago
1995
IEEE
During built-in self-test (BIST), the set of patterns generated by a pseudo-random pattern generator may not provide a sufficiently high fault coverage. This paper presents a new ...
ICCAD
2007
IEEE
14 years 6 months ago
2007
IEEE
While circuit density and power efficiency increase with each major advance in IC technology, reliability with respect to soft errors tends to decrease. Current solutions to this...
DAC
1999
ACM
14 years 1 months ago
1999
ACM
High performance circuit techniques such as domino logic have migrated from the microprocessor world into more mainstream ASIC designs. The problem is that domino logic comes at a...
FPL
1999
Springer
14 years 1 months ago
1999
Springer
This paper details the development, implementation, and results of Synthia, a system for the synthesis of Finite State Machines (FSMs) to field-programmable logic. Our approach us...
VTS
1996
IEEE
14 years 1 months ago
1996
IEEE
Designing a testable circuit is often a two step process. First, the circuit is designed to conform to the functional specifications. Then, the testability aspects are added. By t...