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CADE
2002
Springer
14 years 7 months ago
Formal Verification of a Combination Decision Procedure
Decision procedures for combinations of theories are at the core of many modern theorem provers such as ACL2, Ehdm, PVS, SIMPLIFY, the Stanford Pascal Verifier, STeP, SVC, and Z/Ev...
Jonathan Ford, Natarajan Shankar
AEI
2006
108views more  AEI 2006»
13 years 7 months ago
Grammatical rules for specifying information for automated product data modeling
This paper presents a linguistic framework for developing a formal knowledge acquisition method. The framework is intended to empower domain experts to specify information require...
Ghang Lee, Charles M. Eastman, Rafael Sacks, Shamk...
DATE
2006
IEEE
117views Hardware» more  DATE 2006»
14 years 1 months ago
Formal verification of systemc designs using a petri-net based representation
This paper presents an effective approach to formally verify SystemC designs. The approach translates SystemC models into a Petri-Net based representation. The Petri-net model is ...
Daniel Karlsson, Petru Eles, Zebo Peng
ESORICS
2000
Springer
13 years 11 months ago
Verification of a Formal Security Model for Multiapplicative Smart Cards
Abstract. We present a generic formal security model for operating systems of multiapplicative smart cards. The model formalizes the main security aspects of secrecy, integrity, se...
Gerhard Schellhorn, Wolfgang Reif, Axel Schairer, ...
DAC
2006
ACM
14 years 8 months ago
Early cutpoint insertion for high-level software vs. RTL formal combinational equivalence verification
Ever-growing complexity is forcing design to move above RTL. For example, golden functional models are being written as clearly as possible in software and not optimized or intend...
Xiushan Feng, Alan J. Hu