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» Modeling and Testing Hierarchical GUIs
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DATE
2009
IEEE
129views Hardware» more  DATE 2009»
14 years 2 months ago
Improved performance and variation modelling for hierarchical-based optimisation of analogue integrated circuits
A new approach in hierarchical optimisation is presented which is capable of optimising both the performance and yield of an analogue design. Performance and yield trade offs are ...
Sawal Ali, Li Ke, Reuben Wilcock, Peter Wilson
AUSAI
2008
Springer
13 years 9 months ago
Character Recognition Using Hierarchical Vector Quantization and Temporal Pooling
In recent years, there has been a cross-fertilization of ideas between computational neuroscience models of the operation of the neocortex and artificial intelligence models of mac...
John Thornton, Jolon Faichney, Michael Blumenstein...
EURODAC
1994
IEEE
138views VHDL» more  EURODAC 1994»
13 years 11 months ago
A VHDL-based bus model for multi-PCB system design
In the development of bus-based systems and individual PCB boards interfacing to a bus, the simulation usually requires a specific test bench or creation of quite complex stimuli....
Jari Toivanen, Jari Honkola, Jari Nurmi, Jyrki Tuo...
ICSE
2001
IEEE-ACM
14 years 1 hour ago
A Scalable Formal Method for Design and Automatic Checking of User Interfaces
The paper addresses the formal specification, design and implementation of the behavioral component of graphical user interfaces. The complex sequences of visual events and action...
Jean Berstel, Stefano Crespi-Reghizzi, Gilles Rous...
BVAI
2007
Springer
14 years 1 months ago
Neural Object Recognition by Hierarchical Learning and Extraction of Essential Shapes
We present a hierarchical system for object recognition that models neural mechanisms of visual processing identified in the mammalian ventral stream. The system is composed of ne...
Daniel Oberhoff, Marina Kolesnik