588 search results - page 46 / 118 » Modeling and Verifying Circuits Using Generalized Relative T... |
DAC
2004
ACM
13 years 11 months ago
2004
ACM
This paper presents new technology that accelerates system verification. Traditional methods for verifying functional designs are based on logic simulation, which becomes more tim...
CAV
2000
Springer
14 years 11 days ago
2000
Springer
Address: Abstraction, Composition, Symmetry, and a Little Deduction: The Remedies to State Explosion . . . . . . . . . . . . . . . . . . . . . . . . . . 1 A. Pnueli Invited Address...
PADS
2003
ACM
14 years 1 months ago
2003
ACM
There is a wide-spread usage of hardware design languages(HDL) to speed up the time-to-market for the design of modern digital systems. Verification engineers can simulate hardwa...
ESA
2004
Springer
14 years 1 months ago
2004
Springer
Many network applications that need to distribute content and data to a large number of clients use a hybrid scheme in which one (or more) multicast channel is used in parallel to...
ASPDAC
2005
ACM
13 years 10 months ago
2005
ACM
- To date, most high-level synthesis systems do not automatically solve present design problems, such as those related to timing associated with the physical implementation of mult...