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    CODES
    2008
    IEEE
    171views Software Engineering» more  CODES 2008»
    Model checking SystemC designs using timed automata
    13 years 8 months ago
    Model checking SystemC designs using timed automata
    Download  www.cecs.uci.edu
    SystemC is widely used for modeling and simulation in hardware/software co-design. Due to the lack of a complete formal semantics, it is not possible to verify SystemC designs. In...
    Paula Herber, Joachim Fellmuth, Sabine Glesner
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    RTS
    2006
    176views more  RTS 2006»
    Verifying distributed real-time properties of embedded systems via graph transformations and model checking
    13 years 7 months ago
    Verifying distributed real-time properties of embedded systems via graph transformations and model checking
    Download  www.isis.vanderbilt.edu
    Component middleware provides dependable and efficient platforms that support key functional, and quality of service (QoS) needs of distributed real-time embedded (DRE) systems. C...
    Gabor Madl, Sherif Abdelwahed, Douglas C. Schmidt
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    DAC
    2005
    ACM
    119views Computer Architecture» more  DAC 2005»
    Piece-wise approximations of RLCK circuit responses using moment matching
    13 years 9 months ago
    Piece-wise approximations of RLCK circuit responses using moment matching
    Download  www.cecs.uci.edu
    Capturing RLCK circuit responses accurately with existing model order reduction (MOR) techniques is very expensive. Direct metrics for fast analysis of RC circuits exist but there...
    Chirayu S. Amin, Yehea I. Ismail, Florentin Dartu
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    DAC
    2004
    ACM
    99views Computer Architecture» more  DAC 2004»
    Statistical timing analysis based on a timing yield model
    14 years 8 months ago
    Statistical timing analysis based on a timing yield model
    Download  www.eecs.berkeley.edu
    Starting from a model of the within-die systematic variations using principal components analysis, a model is proposed for estimation of the parametric yield, and is then applied ...
    Farid N. Najm, Noel Menezes
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    DAC
    2005
    ACM
    103views Computer Architecture» more  DAC 2005»
    Simulation of the effects of timing jitter in track-and-hold and sample-and-hold circuits
    13 years 9 months ago
    Simulation of the effects of timing jitter in track-and-hold and sample-and-hold circuits
    Download  www.cs.york.ac.uk
    In this paper, we analyze the effect of jitter in track and hold circuits. The output spectrum is obtained in terms of the system function of the track and hold. It is a fairly g...
    V. Vasudevan
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