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» Modeling and analysis of core-centric network processors
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CCGRID
2007
IEEE
14 years 1 months ago
Reliability Analysis of Self-Healing Network using Discrete-Event Simulation
The number of processors embedded on high performance computing platforms is continuously increasing to accommodate user desire to solve larger and more complex problems. However,...
Thara Angskun, George Bosilca, Graham E. Fagg, Jel...
CASES
2004
ACM
14 years 27 days ago
High-level power analysis for on-chip networks
As on-chip networks become prevalent in multiprocessor systemson-a-chip and multi-core processors, they will be an integral part of the design flow of such systems. With power in...
Noel Eisley, Li-Shiuan Peh
CASES
2006
ACM
14 years 1 months ago
High-level power analysis for multi-core chips
Technology trends have led to the advent of multi-core chips in the form of both general-purpose chip multiprocessors (CMPs) and embedded multi-processor systems-on-a-chip (MPSoCs...
Noel Eisley, Vassos Soteriou, Li-Shiuan Peh
ICS
2009
Tsinghua U.
14 years 1 days ago
A comprehensive power-performance model for NoCs with multi-flit channel buffers
Large Multi-Processor Systems-on-Chip use Networks-on-Chip with a high degree of reusability and scalability for message communication. Therefore, network infrastructure is a cruc...
Mohammad Arjomand, Hamid Sarbazi-Azad
SC
2004
ACM
14 years 27 days ago
A Performance and Scalability Analysis of the BlueGene/L Architecture
This paper is structured as follows. Section 2 gives an architectural description of BlueGene/L. Section 3 analyzes the issue of “computational noise” – the effect that the o...
Kei Davis, Adolfy Hoisie, Greg Johnson, Darren J. ...