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HPCA
2008
IEEE
14 years 9 months ago
System level analysis of fast, per-core DVFS using on-chip switching regulators
Portable, embedded systems place ever-increasing demands on high-performance, low-power microprocessor design. Dynamic voltage and frequency scaling (DVFS) is a well-known techniq...
Wonyoung Kim, Meeta Sharma Gupta, Gu-Yeon Wei, Dav...
EUROPAR
2010
Springer
13 years 9 months ago
Thread Owned Block Cache: Managing Latency in Many-Core Architecture
Abstract. Shared last level cache is crucial to performance. However, multithread program model incurs serious contention in shared cache. In this paper, to reduce average cache ac...
Fenglong Song, Zhiyong Liu, Dongrui Fan, Hao Zhang...
SAC
2009
ACM
14 years 1 months ago
Towards "WYDIWYS" for MIMI using concept analysis
This paper presents a novel software engineering approach for developing a dynamic web interface that meets the quality criterion of “WYDIWYS” - What You Do Is What You See. T...
Jie Dai, Remo Mueller, Jacek Szymanski, Guo-Qiang ...
TVLSI
2010
13 years 3 months ago
Variation-Aware System-Level Power Analysis
Abstract-- The operational characteristics of integrated circuits based on nanoscale semiconductor technology are expected to be increasingly affected by variations in the manufact...
Saumya Chandra, Kanishka Lahiri, Anand Raghunathan...
PPSN
1994
Springer
14 years 25 days ago
Genetic L-System Programming
We present the Genetic L-System Programming (GLP) paradigm for evolutionary creation and development of parallel rewrite systems (Lsystems, Lindenmayer-systems) which provide a com...
Christian Jacob