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» Modeling and evaluation of hardware software designs
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ECBS
2006
IEEE
153views Hardware» more  ECBS 2006»
14 years 4 days ago
A Unified Approach for Verification and Validation of Systems and Software Engineering Models
We present in this paper a unified paradigm for the verification and validation of software and systems engineering design models expressed in UML 2.0 or SysML. This paradigm reli...
Luay Alawneh, Mourad Debbabi, Yosr Jarraya, Andrei...
DATE
2006
IEEE
102views Hardware» more  DATE 2006»
14 years 2 months ago
A systematic IP and bus subsystem modeling for platform-based system design
The topic on platform-based system modeling has received a great deal of attention today. One of the important tasks that significantly affect the effectiveness and efficiency of ...
Junhyung Um, Woo-Cheol Kwon, Sungpack Hong, Young-...
IWANN
1993
Springer
14 years 16 days ago
Hardware Implementations of Artificial Neural Networks
Over the past decade a large variety of hardware has been designed to exploit the inherent parallelism of the artificial neural network models. This paper presents an overview of ...
Dante Del Corso
IJNSEC
2008
106views more  IJNSEC 2008»
13 years 8 months ago
Parallel Hardware Architectures for the Cryptographic Tate Pairing
Identity-based cryptography uses pairing functions,which are sophisticated bilinear maps defined on elliptic curves.Computing pairings efficiently in software is presently a relev...
Guido Marco Bertoni, Luca Breveglieri, Pasqualina ...
BCS
2008
13 years 10 months ago
Hardware Dependability in the Presence of Soft Errors
Using formal verification for designing hardware designs free from logic design bugs has been an active area of research since the last 15 years. Technology has matured and we hav...
Ashish Darbari, Bashir M. Al-Hashimi