A gate level, automated fault diagnosis scheme is proposed for scan-based BIST designs. The proposed scheme utilizes both fault capturing scan chain information and failing test v...
In this survey, we outline basic SAT- and ATPGprocedures as well as their applications in formal hardware verification. We attempt to give the reader a trace trough literature and...
A framework for performance analysis of parallel discrete event simulators is presented. The centerpiece of this framework is a platform-independent Workload Specification Langua...
Vijay Balakrishnan, Peter Frey, Nael B. Abu-Ghazal...
Effective cost estimation is the most challenging activity in software development. Software cost estimation is not an exact science. Cost estimation process involves a series of ...
We propose a novel approach to intelligent tutoring gaming simulations designed for both educational and inquiry purposes in complex multi-actor systems such as infrastructures or...