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HICSS
1995
IEEE
109views Biometrics» more  HICSS 1995»
13 years 11 months ago
The architecture of an optimistic CPU: the WarpEngine
The architecture for a shared memory CPU is described. The CPU allows for parallelism down to the level of single instructions and is tolerant of memory latency. All executable in...
John G. Cleary, Murray Pearson, Husam Kinawi
DATE
2008
IEEE
131views Hardware» more  DATE 2008»
14 years 2 months ago
Parametric Throughput Analysis of Synchronous Data Flow Graphs
Synchronous Data Flow Graphs (SDFGs) have proved to be a very successful tool for modeling, analysis and synthesis of multimedia applications targeted at both single- and multiproc...
Amir Hossein Ghamarian, Marc Geilen, Twan Basten, ...
ISCA
2000
IEEE
91views Hardware» more  ISCA 2000»
14 years 1 days ago
Performance analysis of the Alpha 21264-based Compaq ES40 system
This paper evaluates performance characteristics of the Compaq ES40 shared memory multiprocessor. The ES40 system contains up to four Alpha 21264 CPU’s together with a high-perf...
Zarka Cvetanovic, Richard E. Kessler
ISM
2008
IEEE
110views Multimedia» more  ISM 2008»
14 years 2 months ago
A Hardware-Independent Fast Logarithm Approximation with Adjustable Accuracy
Many multimedia applications rely on the computation of logarithms, for example, when estimating log-likelihoods for Gaussian Mixture Models. Knowing of the demand to compute loga...
Oriol Vinyals, Gerald Friedland
VLDB
2002
ACM
108views Database» more  VLDB 2002»
13 years 7 months ago
Generic Database Cost Models for Hierarchical Memory Systems
Accurate prediction of operator execution time is a prerequisite for database query optimization. Although extensively studied for conventional disk-based DBMSs, cost modeling in ...
Stefan Manegold, Peter A. Boncz, Martin L. Kersten