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ICALP
2009
Springer
14 years 9 months ago
2009
Springer
We initiate the study of sublinear-time algorithms in the external memory model [14]. In this model, the data is stored in blocks of a certain size B, and the algorithm is charged...
CODES
2005
IEEE
14 years 2 months ago
2005
IEEE
Design of programmable processors and embedded applications requires instruction-set simulators for early exploration and validation of candidate architectures. Interpretive simul...
FMSD
2006
13 years 8 months ago
2006
In this paper we present data structures and distributed algorithms for CSL model checking-based performance and dependability evaluation. We show that all the necessary computatio...
IEEEPACT
2006
IEEE
14 years 2 months ago
2006
IEEE
The address sequence on the processor-memory bus can reveal abundant information about the control flow of a program. This can lead to critical information leakage such as encryp...
DATE
2005
IEEE
14 years 2 months ago
2005
IEEE
Conventional cache models are not suited for real-time parallel processing because tasks may flush each other’s data out of the cache in an unpredictable manner. In this way th...