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» Modelling Digital Circuits Problems with Set Constraints
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JAPLL
2010
179views more  JAPLL 2010»
13 years 7 months ago
Tractable query answering and rewriting under description logic constraints
Answering queries over an incomplete database w.r.t. a set of constraints is an important computational task with applications in fields as diverse as information integration and ...
Héctor Pérez-Urbina, Boris Motik, Ia...
DATE
2009
IEEE
147views Hardware» more  DATE 2009»
14 years 3 months ago
Decoupling capacitor planning with analytical delay model on RLC power grid
— Decoupling capacitors (decaps) are typically used to reduce the noise in the power supply network. Because the delay of gates and interconnects is affected by the supply voltag...
Ye Tao, Sung Kyu Lim
IS
2008
13 years 9 months ago
Integration of complex archeology digital libraries: An ETANA-DL experience
In this paper, we formalize the digital library (DL) integration problem and propose an overall approach based on the 5S (streams, structures, spaces, scenarios, and societies) fr...
Rao Shen, Naga Srinivas Vemuri, Weiguo Fan, Edward...
DAC
2003
ACM
14 years 10 months ago
Behavioral consistency of C and verilog programs using bounded model checking
We present an algorithm that checks behavioral consistency between an ANSI-C program and a circuit given in Verilog using Bounded Model Checking. Both the circuit and the program ...
Edmund M. Clarke, Daniel Kroening, Karen Yorav
FMCAD
2007
Springer
14 years 3 months ago
Fast Minimum-Register Retiming via Binary Maximum-Flow
We present a formulation of retiming to minimize the number of registers in a design by iterating a maximum network flow problem. The retiming returned will be the optimum one whi...
Aaron P. Hurst, Alan Mishchenko, Robert K. Brayton