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» Modelling Immunological Memory
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DATE
2002
IEEE
96views Hardware» more  DATE 2002»
14 years 2 months ago
Modeling Techniques and Tests for Partial Faults in Memory Devices
: It has always been assumed that fault models in memories are sufficiently precise for specifying the faulty behavior. This means that, given a fault model, it should be possible...
Zaid Al-Ars, A. J. van de Goor
ACMMSP
2006
ACM
250views Hardware» more  ACMMSP 2006»
14 years 3 months ago
What do high-level memory models mean for transactions?
Many people have proposed adding transactions, or atomic blocks, to type-safe high-level programming languages. However, researchers have not considered the semantics of transacti...
Dan Grossman, Jeremy Manson, William Pugh
KES
2010
Springer
13 years 7 months ago
Evolving takagi sugeno modelling with memory for slow processes
Evolving Takagi Sugeno (eTS) models are optimised for use in applications with high sampling rates. This mode of use produces excellent prediction results very quickly and with lo...
Simon McDonald, Plamen P. Angelov
HIPC
2009
Springer
13 years 6 months ago
A performance prediction model for the CUDA GPGPU platform
The significant growth in computational power of modern Graphics Processing Units(GPUs) coupled with the advent of general purpose programming environments like NVIDA's CUDA,...
Kishore Kothapalli, Rishabh Mukherjee, M. Suhail R...
IESS
2009
Springer
182views Hardware» more  IESS 2009»
13 years 6 months ago
Modeling Cache Effects at the Transaction Level
Abstract. Embedded system design complexities are growing exponentially. Demand has increased for modeling techniques that can provide both accurate measurements of delay and fast ...
Ardavan Pedram, David Craven, Andreas Gerstlauer