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» Modelling Web-Based Instructional Systems
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ISCA
2007
IEEE
162views Hardware» more  ISCA 2007»
14 years 4 months ago
BulkSC: bulk enforcement of sequential consistency
While Sequential Consistency (SC) is the most intuitive memory consistency model and the one most programmers likely assume, current multiprocessors do not support it. Instead, th...
Luis Ceze, James Tuck, Pablo Montesinos, Josep Tor...
SIGMETRICS
2003
ACM
147views Hardware» more  SIGMETRICS 2003»
14 years 3 months ago
Effect of node size on the performance of cache-conscious B+-trees
In main-memory databases, the number of processor cache misses has a critical impact on the performance of the system. Cacheconscious indices are designed to improve performance b...
Richard A. Hankins, Jignesh M. Patel
ECIR
2007
Springer
13 years 11 months ago
Searching Documents Based on Relevance and Type
This paper extends previous work on document retrieval and document type classification, addressing the problem of ‘typed search’. Specifically, given a query and a designated ...
Jun Xu, Yunbo Cao, Hang Li, Nick Craswell, Yalou H...
ICCD
2008
IEEE
221views Hardware» more  ICCD 2008»
14 years 6 months ago
Reversi: Post-silicon validation system for modern microprocessors
— Verification remains an integral and crucial phase of today’s microprocessor design and manufacturing process. Unfortunately, with soaring design complexities and decreasing...
Ilya Wagner, Valeria Bertacco
OOPSLA
2010
Springer
13 years 8 months ago
Hera-JVM: a runtime system for heterogeneous multi-core architectures
Heterogeneous multi-core processors, such as the IBM Cell processor, can deliver high performance. However, these processors are notoriously difficult to program: different cores...
Ross McIlroy, Joe Sventek