The Cell processor is a heterogeneous multi-core processor with one Power Processing Engine (PPE) core and eight Synergistic Processing Engine (SPE) cores. Each SPE has a directly...
Kevin O'Brien, Kathryn M. O'Brien, Zehra Sura, Ton...
— In this paper, we present a novel framework for the automated generation of Network-on-Chips (NoC) architectures, that enables architecture exploration and optimization. The au...
Design of collaborative learning (CL) scenarios is a complex task, but necessary if the goal of the collaboration is learning. Creating well-thought-out CL scenarios requires exper...
In this paper, we investigate the practical performance of lock-free techniques that provide synchronization on shared-memory multiprocessors. Our goal is to provide a technique t...
The C source code associated with the Simulation 101 preconference workshop (offered at the 2006 and 2007 Winter Simulation Conferences) is presented here. This paper begins with ...