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» Modelling Web-Based Instructional Systems
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CF
2006
ACM
14 years 3 months ago
Dynamic thread assignment on heterogeneous multiprocessor architectures
In a multi-programmed computing environment, threads of execution exhibit different runtime characteristics and hardware resource requirements. Not only do the behaviors of distin...
Michela Becchi, Patrick Crowley
RTAS
2005
IEEE
14 years 3 months ago
Timing Analysis for Sensor Network Nodes of the Atmega Processor Family
Low-end embedded architectures, such as sensor nodes, have become popular in diverse fields, many of which impose real-time constraints. Currently, the Atmel Atmega processor fam...
Sibin Mohan, Frank Mueller, David B. Whalley, Chri...
SIGCOMM
2003
ACM
14 years 3 months ago
A knowledge plane for the internet
We propose a new objective for network research: to build a fundamentally different sort of network that can assemble itself given high level instructions, reassemble itself as re...
David D. Clark, Craig Partridge, J. Christopher Ra...
EH
1999
IEEE
351views Hardware» more  EH 1999»
14 years 2 months ago
Evolvable Hardware or Learning Hardware? Induction of State Machines from Temporal Logic Constraints
Here we advocate an approach to learning hardware based on induction of finite state machines from temporal logic constraints. The method involves training on examples, constraint...
Marek A. Perkowski, Alan Mishchenko, Anatoli N. Ch...
IWANN
1997
Springer
14 years 1 months ago
The Pattern Extraction Architecture: A Connectionist Alternative to the Von Neumann Architecture
A detailed connectionist architecture is described which is capable of relating psychological behavior to the functioning of neurons and neurochemicals. The need to be able to bui...
L. Andrew Coward